1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to an improved bit line sense amplifier for reading data stored in memory cells of the semiconductor memory device at a high speed.
2. Description of the Related Art
In a semiconductor memory device, particularly, a dynamic random access memory, data stored in the memory cell, which is selected by a row decoder, is charged or discharged to he bit line connected to a drain of a cell transistor. Information indicated by a voltage difference on the bit line is then sensed and amplified by a sense amplifier connected parallel with the bit line and the sense-amplified Information is outputted to exterior input/output devices. Further, dynamic memory function can be executed as an initial data is restored in the read-out memory cell.
However, the higher the integration density of the memory device and the higher its operational speed thereof is, the smaller its capacitance becomes. This increases of a load by the capacitance of the bit line. Hence, disadvantages arise in that the time required for sensing and amplifying a slight potential difference on the bit line is lengthened, and a data reading speed of the semiconductor memory device is accordingly delayed.
FIG. 1 is a circuit diagram illustrating a configuration of a conventional bit line sense amplifier, which is composed of memory cells MC1 and MC2 respectively connected to word lines WL1 and WL2 and controlled thereby, a sense amplifier 100 shared by the memory cells MC1 and MC2, for sensing and amplifying data stored therein, and Isolation circuits 200 and 300 respectively coupled between each of memory cells MC1 and MC2 and the sense amplifier 100, for electrically connecting or separating the sense amplifier 100 to/from each of memory cells MC1 and MC2 in response to separating control signals ISO1 and ISO2. The sense amplifier 100 includes a p-type sense amplifier 110 driven by a sense amplifier driving signal LA and composed of two PMOS transistors P1 and P2, and an n-type sense amplifier 120 driven by an inverse sense amplifier driving signal LA and composed of two NMOS transistors N1 and N2, thereby sensing and amplifying a potential difference on a bit line pair BL and BL. The bit line pair BL and BL is under the control of a column selection signal CSL, and is electrically separated or connected from/to an input/output line pair IO and IO through a transmission circuit 400 composed of two NMOS transistors 410 and 420.
FIG. 2 is a timing diagram illustrating a data reading operation of the bit line sense amplifier of FIG. 1, by which an operation of the conventional bit line sense amplifier will be given. For example, assuming that the word line WL1 is selected by a row address input, a first isolation gate control signal IS01 is enabled to a logic "high" state and a second isolation gate control signal IS02 is then disabled to a logic "low" state. Accordingly, data of the memory cell MC1 connected to the word line WL1 is loaded in the bit line pair BL and BL through channels of NMOS transistors 210 and 220 as components in the isolation circuit 200. And then, a potential precharged to a prescribed level in the bit line pair BL and BL performs a charge-sharing with the potential of the memory cell MC1 during the period of time t1 of FIG. 2.
Thereafter, if the sense amplifier driving signals LA and LA are respectively enabled to the logic "high" and "low" states, the p-type sense amplifier 100 and n-type sense amplifier 120 are driven to sense and amplify the potential difference on the bit line pair BL and BL during the period of time t2 of FIG. 2. Then, if the column selection signal CSL is enabled to the logic "high" state after a given time duration has elapsed, each of the NMOS transistors 410 and 420, which constitutes the transmission circuit 400, is turned ON so that an amplified potential difference on the bit line pair BL and BL is transmitted to the input/output line pair IO and IO. And then, a developing slope of the potential difference on the bit line pair during the period of time t2 depends on that of sense amplifier driving signals LA and LA.
However, in order to facilitate circuit simplification and high-density memory, only one sense amplifier driving signal generator (not shown) is coupled to a plurality or bit line sense amplifiers to supply the sense amplifier driving signals LA and LA. Therefore, load is significantly increased, thereby causing the developing slope of the sense amplifier driving signals LA and LA to be in a slow state, as shown in FIG. 2. As a result, the developing slope of the potential difference on the bit line pair BL and BL becomes slow, thus reducing a sensing speed. For these reasons, the column selection signal has to be enabled after the time required for developing the potential difference on the bit line pair and must be extended by a given time duration, so that data on the bit line pair BL and BL can be exactly transmitted to the input/output lines pair IO and IO without error through the transmission circuit 400 Generally, the length of the input/output lines pair IO and IO is mush grater than that of the bit line pair BL and BL. Therefore, their parasitic capacitance is ten times as large as that of the bit line. The input/output lines pair IO and IO is precharged to a given level before the column selection signals is enabled to the logic "high" slate, but herein, it is assumed that the input/output lines pair IO and IO is precharged to Vcc-Vt level.
An operation that the bit line pair BL and BL performs a charge-sharing with the input/output lines pair IO and IO during the period of time t3 of FIG. 2, will be described hereinbelow. As shown in FIG. 2, when the column selection signal is enabled to the logic "high" state before the potential difference on the bit line pair BL and BL is fully developed, since the bit line pair BL and BL shares charge with the input/output line pair IO and IO having relative large parasitic capacitance, a potential difference .increment.VbL on the bit line pair BL and BL is temporarily decreased by a given voltage. Accordingly, the developing speed of the potential difference on the input/output lines pair IO and IO is delayed by the period of time required for re-developing the reduced potential difference.
On the other hand, since the input/output line pair has a large parasitic capacitance and the developing slope of sense amplifier driving signals LA and LA is in a slow state, the developing slope of the input/output line pair is also in a slow state, as shown in the period of time t3 of FIG. 2, wich significantly delayed a data output operation. In particular, in the art of DRAM (Dynamic Random Access Memory), this acts as an impediment in reducing the time tRAC required for outputting effective data after receiving a row address strove signal RAS. In other words, since the period of time t2 required for enabling the column selection signal CSL after fully developing the potential difference .increment.VbL on the bit line pair, and the period of time t3 required for amplifying a potential difference .increment.ViO through an input/output sense amplifier (not shown) after fully developing the potential difference .increment.Vio on the input/output line pair IO and IO are inevitably necessary, an overall data reading speed in a memory device is accordingly decreased. Further, since precharging of the input/output line pair is performed when an input of a non-effective column address is changed into an input of the effective column address, if an equalization of the input/output line pair IO and IO is incomplete, the development of the potential difference thereon is significantly delayed by the effective data on the bit line pair, and accordingly the data reading speed of the memory device is also delayed.